1. Field of the Invention
The present invention relates to a read operation technique for reading data held in a nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a flash memory store data by having electrons injected into the insulators of their memory cells for changes in threshold voltage. The memory cells rise in threshold voltage when their insulators contain electrons, and fall when the insulators contain no electron. When the memory cells of a flash memory are to store binary data, a state of high threshold voltage where no current flows through the memory cells in read operations is the state where xe2x80x9cdata 0xe2x80x9d is written (xe2x80x9c0 statexe2x80x9d). A state of low threshold voltage where currents flow through the memory cells in read operations is the state where xe2x80x9cdata 1xe2x80x9d is written (xe2x80x9c1 statexe2x80x9d).
The xe2x80x9c0 statexe2x80x9d and the xe2x80x9c1 statexe2x80x9d are detected by comparing the currents flowing through the memory cells in read operations (memory cell current) with a reference current.
Nonvolatile semiconductor memories of this type are ever growing in memory capacity (memory density) year by year. As a technique for increasing the memory density, level multiplication has been proposed of memory cells. To store multileveled data into each single memory cell, however, the amount of electrons to be injected into the memory cell must be precisely adjusted to secure read margins. In general, it is difficult to adjust the amount of injection of electrons precisely. In the case of storing multileveled data into memory cells by using this technique, small variations in the semiconductor processes can easily cause a drop in yield. Moreover, to store multileveled data into the memory cells, a plurality of reference currents are required for the sake of detecting the logical values of the data. In the meantime, techniques in which the integration level of memory cells is raised by raising the integration level of word lines to heighten storage density have been disclosed in Japanese Unexamined Patent Application Publication No. Hei 2-231772 and so on.
FIG. 1 shows the cell structure of a memory cell array in a nonvolatile semiconductor memory disclosed in this kind of publication.
This nonvolatile semiconductor memory is characterized in that second word lines WL2 having a wiring width different from that of first word lines WL1 are arranged in between these first word lines WL1. The first and second word lines WL1 and WL2, lying over memory cells, function as control gates. Formed under the control gates are floating gates which are shown shaded in the diagram. The floating gates are formed on a silicon substrate via an oxide film, in between bit lines BL which are made of a diffusion layer.
In the diagram, the sources S and drains D of cell transistors (hereinafter, referred to as first memory cells) are formed at the intersections of the first word lines WL1 and the bit lines BL. Then, the channel regions CH of the first memory cells are formed between the sources S and the drains D. Similarly, the sources S and drains D of cell transistors (hereinafter, referred to as second memory cells) are formed at the intersections of the second word lines WL2 and the bit lines BL. The channel regions CH of the second memory cells are formed between the sources S and the drains D.
In this nonvolatile semiconductor memory, after the first word lines WL1 and the floating gates corresponding to these word lines WL1 are formed, the second word lines WL2 and the floating gates corresponding to these second word lines WL2 are formed in the gaps between the first word lines WL1. On that account, the gate width W2 of the second memory cells MC2 becomes smaller than the gate width W1 of the first memory cells MCI. As for the channel lengths (the intervals between the sources S and drains D), the first memory cells MC1 and the second memory cells MC2 are identical to each other.
FIG. 2 shows an equivalent circuit of the memory cell array shown in FIG. 1.
A plurality of first memory cells MC1 are connected in series along the first word lines WL1. The sources S and drains S (data input/output nodes) of adjoining memory cells MC1 are connected to respective common bit lines BL. A plurality of second memory cells MC2 are connected in series along the second word lines WL2. The sources S and drains D (data input/output nodes) of adjoining memory cells MC2 are connected to common bit lines BL This kind of memory cell array is generally referred to as a memory cell array of virtual ground type.
FIG. 3 shows an overview of the read operations of data retained in the memory cells of the nonvolatile semiconductor memory described above.
To read data from a first memory cell MC1, the first word line connected to this memory cell MC1 is supplied with a read voltage of, e.g., 2.5 V. The bit lines BL connected to the source and drain of the first memory cell are supplied with 0 V and 5 V. When the first memory cell MC1 is in the xe2x80x9c0 statexe2x80x9d, the memory cell turns off due to its high threshold voltage, so that no memory cell current flows between the bit lines BL. When the first memory cell MC1 is in the xe2x80x9c1 statexe2x80x9d, the memory cell turns on due to its low threshold voltage, so that a memory cell current flows between the bit lines BL.
Similarly, to read data from a second memory cell MC2, a read voltage of 2.5 V is supplied to a second word line WL2, and 0V and 5V are supplied to bit lines BL on both sides of the second memory cell MC2. When the second memory cell MC2 is in the xe2x80x9c0 statexe2x80x9d, no memory cell current flows. When the second memory cell MC2 is in the xe2x80x9c1 statexe2x80x9d, a memory cell current flows. Then, the memory cell current is compared with a reference current IREF to detect whether the xe2x80x9c0 statexe2x80x9d or the xe2x80x9c1 statexe2x80x9d the memory cell MC1 (or MC2) retains.
Nevertheless, as described above, the gate width WI of the first memory cells MC1 is different from the gate width W2 of the second memory cells MC2. The values of the memory cell currents at the turning-on of the cell transistors of the memory cells MC1 and MC2 depend on the ratios W/L between the gate widths W and channel lengths L of the cell transistors. Accordingly, in xe2x80x9c1 statexe2x80x9d read, the memory cell current of the second memory cells MC2 become smaller than that of the first memory cells MC1.
The reference current IREF needs to be set at between the maximum value and the minimum value of the memory cell currents. This requires that the reference current IREF be set in accordance with the second memory cells MC2 which have a smaller memory cell current in the xe2x80x9c1 statexe2x80x9d. As a result, in the first memory cells MC1, the xe2x80x9c0 statexe2x80x9d read margin M0 becomes smaller than the xe2x80x9c1 statexe2x80x9d read margin M1 with a problem of lower reliability.
Conventionally, there has not been proposed any reliable technique for reading data retained in the memory cells of a nonvolatile semiconductor memory that has a plurality of word lines of different wiring widths (gate widths).
It is an object of the present invention to provide a nonvolatile semiconductor memory having a plurality of word lines of different-wiring widths in which data retained in the memory cells is read with reliability.
It is another object of the present invention to provide a nonvolatile semiconductor memory of virtual ground type in which data retained in the memory cells is read with reliability.
According to one of the aspects of the present invention, memory cell currents flowing through memory cells during data readout are compared with reference currents that are set in accordance with the wiring widths of word lines connected to the memory cells. Then, depending on whether larger or smaller the memory cell currents are than the reference currents, the logic levels of data retained in the memory cells are detected. The word lines also function as control gates of the cell transistors of the memory cells. That is, the wiring widths of the word lines correspond to the gate widths of the cell transistors so that the greater the wiring widths of the word lines are, the lower the ON resistances of the cell transistors become. As a reslt, the values of the memory cell curernts that flow in read operations vary with the wiring widths of the word lines. Setting the reference currents according to the wiring widths of the word lines allows the reference currents to be set at optimum values for the respective memory cells having different gate widths from each other.
For example, when the memory cells are to store binary data, the reference currents for the memory cells having different gate widths are set to the respective middle values between the memory cell currents that flow in reading xe2x80x9clogic 1xe2x80x9d and the memory cell currents that flow in reading xe2x80x9clogic 0xe2x80x9d. Since the reference currents are set in accordance with the characteristic of memory cells, it is possible to improve the read margins for enhanced reliability in read operations.
The nonvolatile semiconductor memory has, for example, a plurlaty of first word lines arranged with intervals and a plurlaity of second word lines arranged in the respective intervals of these first word lines. The wiring width of the first word lines and the wiring width of the second word lines are different from each other. First memory cells are connected to the first word lines. Second memory cells are connected to the second word lines. The first and second memory cells have, for example, a floating gate for storing electric charge or a trap gate for trapping electric charge.
Then, in reading data from the first memory cell, a memory cell current flowing through this first memory cell is compared with the first reference current to detect the logic level of data retained in the first memory cell. In reading data from the second memory cell, a memory cell current flowing through this second memory cell is compared with the second reference current different from the first reference current to detect the logic level of data retained in the second memory cell.
According to another aspect of the present invention, a first word line is connected to a control gate of a first memory cell which is nonvolatile. A second word line having a wiring width different from that of the first word line is connected to a control gate of a second memory cell which is nonvolatile.
In reading data from the first memory cell, the first word line is supplied with a first voltage, and a memory cell current flowing through this first memory cell is compard with a reference current to detect the logic level of data retained in the first memory cell. In reading data from the second memory cell, the second word line is supplied with a second voltage different from the first voltage, and a memory cell current flowing through this second memory cell is compared with the reference current to detect the logic level of data retained in the second memory cell.
For example, the first voltage and the second voltage are set so that the memory cell currents flowing through the first and second memory cells coincide with each other when data retained in the first and second memory cells has the same logic level. Specifically, if the memory cells are to store binary data, the first voltage and the second voltage are set so that the memory cell currents flowing through the first and second memory cells coincide with each other when the first and second memory cells are programmed for low threshold voltages. Since the memory cell currents of the first and second memory cells (first and second word lines) having different gate widths (wiring widths) can be equal to each other, only a single refrence current is needed for deciding the logic levels of data. As a result, the generator of the reference current can be simply configured, allowing a reduction in the chip size of the nonvolatile semiconductor memory.
By means of the first and second voltages, the memory cell currents of the first and second memory cells corresponding to data of the same logic level can be equal. Therefore, the read margin of the first and second memory cells can be made identical.
According to another aspect of the present invention, first word lines are connected to control gates of first memory cells which are nonvolatile. Second word lines having a wiring width different from that of the first word lines are connected to contorl gates of second memory cells which are nonvolatile. The data written to the nonvolatile semiconductor memory is retained as multileveled data in a pair of first and second memory cells. That is, the pair of first and second memory cells funciton as a multilevel memory cell for retaining multileveled data. When the first and second memory cells retain binary data each, four-level data can be read/written from/to the multilevel memory cell.
In a read operation, the first and second word lines are selected, and memory cell currents corresponding to the respective pieces of data retained in the first and second memory cells flow through the first memory cell and the second ememory cell, respectively. The total amount of memory cell currents flowing through the first and second memory cells (the memory cell current of the multilevel memory cell) is compared with each of a plrualty of reference currents to detect the logic level of the multileveled data.
In conventional memory cells for retaining multileveled data, data was written with the threshold voltages of the memory cells controlled by such means as adjustments to the injection amount of electrons, and the memory cell currents which occurred depending on the threshold voltages were compared with each of a plurality of reference currents. In the present invention, binary data is written to each of the first and second memory cells having different gate widths, and at the time of reading the data, the memory cell currents which occur depending on the shapes (gate widths) of the preformed memory cells are compared with each of a plurality of reference currents. That is, the characteristics of the memory cell made in advance can be utilized to perform read and write operations. Thus, multileveled data can be easily written without a complicated control, improving the read margins at the same time.
According to another aspect of the present invention, a pair of first and second memory cell function as a multilevel memory cell for retaining multileveled data. For example, a first voltage to be supplied to the first word line connected to the first memory cell and a second voltage to be supplied to the second word line connected to the first memory cell are set so that the memory cell currents flowing through the first and second memory cells coincide with each other when data retained in the first and second memory cells has the same logic level. That is, either one of the memory cell currents flowing the first and second memory cells is increased by the first voltage or the second voltage. As a result, the multilevel memory cell configured of the first and second memory cell can be improved in read margin for enhanced reliability in read operations.